Texas Instruments Placement Papers – Texas Instruments Previous Placement Papers pdf

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texas instruments placement papers for electronics with answers contains different types of questions from different topics like Aptitude, reasoning. Basic programing language questions and simple grammar questions. By referring S texas instruments placement papers for analog design engineer questions candidates get clear idea about what type of questions asking in the online test. So candidates who are searching for the texas instruments placement papers for electronics are now download from the below links. Here we are providing texas instruments placement papers analog as the special reference. These texas instruments placement papers are very useful for the candidates who are going to attend the texas instruments placements. Here we also providing texas instruments previous placement papers for the candidate’s reference.

About Texas Instruments

Texas Instruments semiconductor innovations help 90,000 customers unlock the possibilities of the world as it could be – smarter, safer, greener, healthier and more fun. Our commitment to building a better future is ingrained in everything we do – from the responsible manufacturing of our semiconductors, to caring for our employees, to giving back inside our communities. This is just the beginning of our story.

Some texas instruments placement papers questions

1. (steeper transition) by:

  1. Increasing W/L of PMOS transistor
  2. Increasing W/L of NMOS transistor
  3. Increasing W/L of both transistors by the same factor
  4. Decreasing W/L of both transistor by the same factor

2. Minimum number of 2-input NAND gates that will be required to implement the function: Y = AB + CD + EF is

  1. 4
  2. 5
  3. 6
  4. 7

3. Consider a two-level memory hierarchy system M1 & M2. M1 is accessed first and on miss M2 is accessed. The access of M1 is 2 nanoseconds and the miss penalty (the time to get the data from M2 in case of a miss) is 100 nanoseconds. The probability that a valid data is found in M1 is 0.97. The average memory access time is:

  1. 94 nanoseconds
  2. 06 nanoseconds
  3. 00 nanoseconds
  4. 06 nanoseconds

4. Interrupt latency is the time elapsed between:

  1. Occurrence of an interrupt and its detection by the CPU
  2. Assertion of an interrupt and the start of the associated ISR
  3. Assertion of an interrupt and the completion of the associated ISR
  4. Start and completion of associated ISR

5. Which of the following is true for the function (A.B + A’.C + B.C)

  1. This function can glitch and can be further reduced
  2. This function can neither glitch nor can be further reduced
  3. This function can glitch and cannot be further reduced
  4. This function cannot glitch but can be further reduced

6. For the two flip-flop configuration below, what is the relationship of the output at B to the clock frequency?

  1. Output frequency is 1/4th the clock frequency, with 50% duty cycle
  2. Output frequency is 1/3rd the clock frequency, with 50% duty cycle
  3. Output frequency is 1/4th the clock frequency, with 25% duty cycle
  4. Output frequency is equal to the clock frequency

7. The voltage on Node B is:

  1. 0
  2. 10
  3. –10

8. A CPU supports 250 instructions. Each instruction op-code has these fields:

The instruction type (one among 250)

  1. A conditional register specification
  2. 3 register operands
  3. Addressing mode specification for both source operands

9. The CPU has 16 registers and supports 5 addressing modes. What is the instruction op-code length in bits?

  1. 32
  2. 24
  3. 30
  4. 36

10. In the iterative network shown, the output Yn of any stage N is 1 if the total number of 1s at the inputs starting from the first stage to the Nth stage is odd. (Each identical box in the iterative network has two inputs and two outputs). The optimal logic structure for the box consists of:

  1. One AND gate and one NOR gate
  2. One NOR gate and one NAND gate
  3. Two XNOR gates
  4. One XOR gate

11. Consider a circuit with N logic nets. If each net can be stuck-at either values 0 and 1, in how many ways can the circuit be faulty such that only one net in it can be faulty, and such that up-to all nets in it can be faulty?

  1. 2 and 2N
  2. N and 2^N
  3. 2N and 3^N-1
  4. 2N and 3N

12. In the circuit shown, all the flip-flops are identical. If the set-up time is 2 ns, clock->Q delay is 3 ns and hold time is 1 ns, what is the maximum frequency of operation for the circuit?

  1. 200 MHz
  2. 333 MHz
  3. 250 MHz
  4. None of the above

13. Which of the following statements is/are true? Combinational circuits may have feedback, sequential circuits do not. Combinational circuits have a ‘memory-less’ property, sequential circuits do not.

III. Both combinational and sequential circuits must be controlled by an external clock.

  1. I only
  2. II and III only
  3. I and II only
  4. II only

14. Consider an alternate binary number representation scheme, wherein the number of ones M, in a word of N bits, is always the same. This scheme is called the M-out-of-N coding scheme. If M=N/2, and N=8, what is the efficiency of this coding scheme as against the regular binary number representation scheme? (As a hint, consider that the number of unique words represent able in the latter representation with N bits is 2^N. Hence the efficiency is 100%)

  1. Close to 30%
  2. Close to 50%
  3. Close to 70%
  4. Close to 100%

15. A CPU supports 4 interrupts- I1, I2, I3 and I4. It supports priority of interrupts. Nested interrupts are allowed if later interrupt is higher priority than previous one. During a certain period of time, we observe the following sequence of entry into and exit from the interrupt service routine:


From this sequence, what can we infer about the interrupt routines?

  1. I3 > I4 > I2 > I1
  2. I4 > I3 > I2 > I1
  3. I2 > I1; I3 > I4 > I1
  4. I2 > I1, I3 > I4 > I2 > I1

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